Scientist / Team Leader � Advanced Packaging This position deals with the establishment of advanced interconnection and packaging platform, the design and development of advanced interconnection methods and packaging scheme for electronic devices with emphasis on Flip chip, Micro-bump, chip stacking and embedded Wafer Level Packaging. Responsibilities: The key responsibility will include micro-joint design using solder/Cu pillar, process integration for advanced packaging using Through Silicon Via, Multiple die stacking and embedded wafer level packaging. Requirements: � PhD degree in Mechanical engineering or Material science with at least 6 years of relevant experience. Candidate with more years of relevant experience may be offered a leader/technical management position � Experience in wafer level processes, such as Through Silicon Via, RDL and bumping and packaging assembly processes, such as Flip-chip, underfilling and wafer level molding � Good knowledge of packaging materials and processes � Hands-on experience on micro-interconnection and reliability analysis � Experience in project scoping and execution � Self-motivated and proactive team player with ability to work in a multidisciplinary team � Excellent analytical and problem solving skills Contact: Eisa Teoh Institute of Microelectronics (IME) 11 Science Park Road Singapore Science Park II Singapore, Singapore 117685 Singapore Phone: 65-67705351 Fax: 65-67731912 Email: personnelime.a-star.edu.sg
